Search cycle time and search latency are two factors that influence the efficiency of content addressable memory (CAM) devices when processing consecutive search instructions. Unfortunately, many techniques to reduce search cycle time and/or search latency often lead to significant increases in power consumption, particularly when a large number of CAM array blocks within a multi-block CAM core are searched in parallel. To address this problem of excessive power consumption, techniques have been developed to convert a global search operation within a CAM core into a plurality of “segmented” search operations performed on corresponding segments of the CAM core. Unfortunately, techniques to convert a global search operation into a plurality of lower power search operations performed sequentially can result in a significant increase in search latency associated with each global search operation. Other techniques to address excessive power consumption include lowering match line power requirements during each search cycle by reducing match line voltage fluctuations during precharge and discharge intervals within each search operation.